[myhdl-list] Programmable LFSR

[Joseph C. <ca...@au...>]

I am attempting to parameterize the creation of Galois LFSRs.  I have a table that contains Galois polynomials (a list of tuples named GALOIS_TABLE).  The following is my first attempt at a solution in MyHDL. 

def Galois(out, clk, rst, width=32):
	'''
	Implement a Galois Linear Feedback Shift Register (LFSR).

	Parameters
	----------
	width : integer
		The length of the LFSR

	Input Ports
	-----------
	clk : The clock
	rst : Active high reset
	
	Output Ports
	------------
	out : Pseudo-Random word
	'''
	sel_table = width - 3
	polynomial = GALOIS_TABLE[sel_table]
	polynomial = polynomial[1:len(polynomial)-1]  # Take the relevant part of the polynomial

	state = Signal(intbv(0)[width:])

	@always(clk.posedge, rst.negedge)
	def logic():
		if rst == 1:
			state.next[0] = 1
		else:
			state.next[width-1] = state[0]
			for i in downrange(width-1, 0):
				if i in polynomial:  # This is where the problem occurs, I believe
					state[i].next = state[i+1] ^ state[0]
				else:
					state[i].next = state[i+1]
	
	@always_comb
	def assignments():
		out.next = state		

	return logic, assignments


--------------------------------------------------------------------------------------------------------------------
I do not think the "if i in whatever" syntax is convertible.  I was wondering if anyone had any
suggestions on alternative Python code that would yield a convertible example.  Attempting
to convert the above code gives the following stack trace using Python 2.6.2:

  File "galois.py", line 147, in <module>
    galois = toVerilog(Galois, out, clk, rst, width=18)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 124, in __call__
    _convertGens(genlist, vfile)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 321, in _convertGens
    v.visit(tree)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1248, in visit_Module
    self.visit(stmt)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1850, in visit_FunctionDef
    self.visit_stmt(node.body)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
    self.visit(stmt)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1177, in visit_If
    self.mapToIf(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1232, in mapToIf
    self.visit_stmt(node.else_)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
    self.visit(stmt)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1140, in visit_For
    self.visit_stmt(node.body)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
    self.visit(stmt)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1177, in visit_If
    self.mapToIf(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1221, in mapToIf
    self.visit(test)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 969, in visit_Compare
    self.write(" %s " % opmap[type(node.ops[0])])
KeyError: <class '_ast.In'>


--------------------------------------------------------------------------------------------------------------------
For width=18,  a Galois polynomial is x^18 + x^11 + 1.  The target 
Verilog should behave as below:

module galois18(state, clk, rst);
	input clk;
	input rst;
	output [17:0] state;
	reg [17:0] state;

	always @(posedge clk) begin
		if(~rst) begin
			state <= {state[0], state[17:12], state[11]^state[0], state[10:1]};
		end
		else begin
			state[0] <= 1;
		end
	end
endmodule



Joseph