Re: [myhdl-list] simulation semantics
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jandecaluwe
From: Jan D. <ja...@ja...> - 2009-07-18 09:32:30
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Geoffrey Brown wrote: > I've been creating little examples to see if I understand the semantics > of myhdl. > I came across one where the behavior differs completely depending > upon the initial value of a signal (no problem there), but the generated > verilog > is identical There is an issue with initial values and conversion, and it's listed as an open task. For more info: http://www.myhdl.org/doku.php/dev:tasks#initial_values_support -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com |