Re: [myhdl-list] Combinational Logic Modeling

[Jan D. <ja...@ja...>]

Joseph Cali wrote:
> You are correct that Example 2 can be solved with an MSB detector 
> (not only solved, but solved more efficiently) and in that sense it is  
> not an ideal example.  The general form of the question is how to write 
> large combinational encoders and decoders in myhdl where neither the 
> input nor the output are binary.  I will look at the EnumItem suggestion 
> in the coming days.

Please be precise in what you are asking. You original post mentioned
"how to implement in MyHDL" but from the context I inferred you were
asking how to *convert* a *specific* design problem from MyHDL to
Verilog, probably for synthesis. Now you suggest your example was only
meant to illustrate a general case. If you want meaningful feedback,
don't make me guess.

There's a *very* big difference between

1) modeling
2) conversion to Verilog/VHDL
3) synthesis

Modeling in MyHDL is intended to be completely general in the Python
sense. Much, much more powerful than Verilog.

Conversion is very restrictive. Synthesis is even more restrictive.
Moreover, I can't control synthesis contraints.

My goal with conversion is the following: whatever you may want to
write in Verilog *for synthesis*, should be easier or as easy to do
with MyHDL. But there's no way in which MyHDL can magically avoid
synthesis restrictions. Therefore, if synthesis is your concern,
you should also understand synthesis itself quite well.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com