Re: [myhdl-list] Combinational Logic Modeling

[Joseph C. <ca...@au...>]

You are correct that Example 2 can be solved with an MSB detector 
(not only solved, but solved more efficiently) and in that sense it is  
not an ideal example.  The general form of the question is how to write 
large combinational encoders and decoders in myhdl where neither the 
input nor the output are binary.  I will look at the EnumItem suggestion 
in the coming days.

I am more than willing to provide examples that show other design 
problems not directly addressed in the existing examples.  The
examples provided on the myhdl site are excellent but having 
extra examples cannot hurt.  

I intended to preface my first e-mail by stating that I would be 
traveling early this week and not have Internet access.

Thanks for the help,
Joseph


>>> Jan Decaluwe <ja...@ja...> 07/14/09 4:46 AM >>>
Your examples clearly have a logic structure. In such cases, I think it's
often better to use that structure instead of look-up tables.
Look-up tables are ideal for unstructured logic values.

Example 1 is apparently nothing else than  (1 << address) - 1.

Example 2 is interesting, it can be solved with an msb detector. It is in example
I would consider putting on the website, because it may show some interesting
convertor features.

Just loop over de bit indices from high to low. As soon as a 1 is found,
assign the current index to the result and break out of the loop.

In Verilog, this is awkward, because you need to use named blocks and
disable statements. However, the MyHDL convertor can do this automatically.
Many people probably don't realize that this is perfectly
synthesizable (expecially because of the awkwardness in Verilog) so
it may be a good example of how MyHDL can help.

Jan


Joseph Cali wrote:
> I understand how to implement the following in MyHDL (this was generated using toVerilog):
> 
> ----------------------------------------------------------------------------------
> module binary2thermometer (
>     value,
>     address
> );
> 
> output [30:0] value;
> reg [30:0] value;
> input [4:0] address;
> 
> always @(address) begin: BINARY2THERMOMETER_READ
>     // synthesis parallel_case full_case
>     case (address)
>         0: value <= 1;
>         1: value <= 3;
>         3: value <= 15;
>         4: value <= 31;
>         5: value <= 63;
>         6: value <= 127;
>         7: value <= 255;
>         8: value <= 511;
>         9: value <= 1023;
>         10: value <= 2047;
>         11: value <= 4095;
>         12: value <= 8191;
>         13: value <= 16383;
>         14: value <= 32767;
>         15: value <= 65535;
> 	.
> 	.
> 	.
> 	endcase
> end
> endmodule
> ----------------------------------------------------------------------------------
> 
> But how would I model the inverse in MyHDL (this was not done through MyHDL):
> 
> ----------------------------------------------------------------------------------
> module thermometer2binary (
>     value,
>     address
> );
> 
> output [4:0] value;
> reg [4:0] value;
> input [30:0] address;
> 
> always @(address) begin: BINARY2THERMOMETER_READ
>     // synthesis parallel_case full_case
>     case (address)
>         1: value <= 1;
>         3: value <= 2;
>         15: value <= 3;
>         31: value <= 4;
>         63: value <= 5;
>         127: value <= 6;
>         255: value <= 7;
>         511: value <= 8;
>         1023: value <= 9;
>         2047: value <= 10;
>         4095: value <= 11;
>         8191: value <= 12;
>         16383: value <= 13;
>         32767: value <= 14;
>         65535: value <= 15;
> 	.
> 	.
> 	.
> 	endcase
> end
> endmodule
> ----------------------------------------------------------------------------------
> 
> Also, have you considered using Python dictionaries to infer ROMs and other large combinational logic instead of tuples?  I recently stumbled upon MyHDL and I immediately connected with the idea.
> 
> Thanks for the help.
> 
> ------------------------------------------------------------------------------
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com


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