[myhdl-list] Combinational Logic Modeling
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jandecaluwe
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From: Joseph C. <ca...@au...> - 2009-07-12 15:12:16
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I understand how to implement the following in MyHDL (this was generated using toVerilog):
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module binary2thermometer (
value,
address
);
output [30:0] value;
reg [30:0] value;
input [4:0] address;
always @(address) begin: BINARY2THERMOMETER_READ
// synthesis parallel_case full_case
case (address)
0: value <= 1;
1: value <= 3;
3: value <= 15;
4: value <= 31;
5: value <= 63;
6: value <= 127;
7: value <= 255;
8: value <= 511;
9: value <= 1023;
10: value <= 2047;
11: value <= 4095;
12: value <= 8191;
13: value <= 16383;
14: value <= 32767;
15: value <= 65535;
.
.
.
endcase
end
endmodule
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But how would I model the inverse in MyHDL (this was not done through MyHDL):
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module thermometer2binary (
value,
address
);
output [4:0] value;
reg [4:0] value;
input [30:0] address;
always @(address) begin: BINARY2THERMOMETER_READ
// synthesis parallel_case full_case
case (address)
1: value <= 1;
3: value <= 2;
15: value <= 3;
31: value <= 4;
63: value <= 5;
127: value <= 6;
255: value <= 7;
511: value <= 8;
1023: value <= 9;
2047: value <= 10;
4095: value <= 11;
8191: value <= 12;
16383: value <= 13;
32767: value <= 14;
65535: value <= 15;
.
.
.
endcase
end
endmodule
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Also, have you considered using Python dictionaries to infer ROMs and other large combinational logic instead of tuples? I recently stumbled upon MyHDL and I immediately connected with the idea.
Thanks for the help.
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