Re: [myhdl-list] a few questions relating to recursive designs

[Geoffrey B. <geo...@gm...>]

I haven't downloaded the development snapshot, but I'm pretty certain
that what you have designed will work -- either bottom up by concatenating
signals or top down by splitting signals.

In my heart, I wish the extra syntax wasn't needed; however, I take your
point about the efficiency of compiled vs interpreted simulation with
respect
to compound signals.

In any case, I appreciate the effort you've taken in reaction to
the demands of your user community

Geoffrey

On Tue, Jun 23, 2009 at 4:51 AM, Jan Decaluwe <ja...@ja...> wrote:

> Geoffrey Brown wrote:
> > I thought I'd plunge in with a recursive structure (an N-way mux) which
> > follows.  I'm embarrassed
> > how long it took me to figure this out.   Now here are a few questions.
> >
> > 1)  I wanted to use a selector both as a bit vector and an integer.
> > Naturally
> >    I made a signal from an intbv, but found the hard way that the obvious
> >    thing, picking off bits by slicing, doesn't give you what is needed
> > (in this
> >    context) -- another signal which has a subset of the bits from the
> > original
> >
>
> Geoffrey:
>
> Please check whether a _SliceSignal would solve your problem:
>
> http://www.myhdl.org/doku.php/meps:mep-105
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
>
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