Re: [myhdl-list] verilog conversion bug ?

[Geoffrey B. <geo...@gm...>]

No testbench -- I just simulated with the VCD file generated by the myhdl
module.   So the simulation output of myhdl became the driver for quartus.


Geoffrey

On Sat, Jun 13, 2009 at 9:39 AM, Felton Christopher
<chr...@gm...>wrote:

> On Jun 12, 2009, at 2:33 PM, Geoffrey Brown wrote:
>
> > The following is an attempt to create a simple PWM module.   When I
> > simulate in myhdl and simulate the generated verilog in quartus,
> > I get different results.  Specifically the "pulse" output is delayed
> > one clock period in quartus which suggests that my use of
> > count.next in myhdl doesn't translate into semantically equivalent
> > verilog.  Clearly, I can rewrite things to get the behavior
> > I want, but I'm worried about the inconsistency.
>
> Do you have your Verilog testbench for Quartus, think it might be is
> mismatch in your testbenches and not the pwm module.  Does you clken
> change on the falling edge of clock in your Verilog testbench as well?
>
> Chris
>
>
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