Re: [myhdl-list] verilog conversion bug ?

[Felton C. <chr...@gm...>]

On Jun 12, 2009, at 2:33 PM, Geoffrey Brown wrote:

> The following is an attempt to create a simple PWM module.   When I  
> simulate in myhdl and simulate the generated verilog in quartus,
> I get different results.  Specifically the "pulse" output is delayed  
> one clock period in quartus which suggests that my use of
> count.next in myhdl doesn't translate into semantically equivalent  
> verilog.  Clearly, I can rewrite things to get the behavior
> I want, but I'm worried about the inconsistency.

Do you have your Verilog testbench for Quartus, think it might be is  
mismatch in your testbenches and not the pwm module.  Does you clken  
change on the falling edge of clock in your Verilog testbench as well?

Chris