Re: [myhdl-list] future improvements suggestion

[Jan D. <ja...@ja...>]

Xiang Li wrote:
> During the period that I was using MyHDL. I think there might be a 
> improvement in the future, maybe it can be another open task. As we have 
> seen that in verilog. we will define the module name and the associated 
> input/output pins like below:

One module's input is always another module's output :-)

As you use MyHDL for modeling and conversion, you will note that
it works well without input/output declarations. In fact, the only
thing what could we do with this is to check whether usage
and declaration match. This may make sense, but it is not the
philosophy of dynamic languages such as Python. In other words,
it's fine for VHDL/Verilog, but not for a Python-based HDL.

I'm agree that this info is useful for human readers. The Python way is
to document parameter and their purpose in the docstring of
a function. For examples see:
    http://www.myhdl.org/doku.php/cookbook:intro

Jan


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