[myhdl-list] future improvements suggestion

[Xiang Li <u46...@an...>]

During the period that I was using MyHDL. I think there might be a improvement in the future, maybe it can be another open task. As we have seen that in verilog. we will define the module name and the associated input/output pins like below:

module modulename(
                                    pinname1,
                                    pinname2,
                                    ...
                                   );
input  pinname1;
output pinname2;
...

But in MyHDL, we define it like this
def modulename(pinname1, pinname2,...):

Obviously, MyHDL lack of a corresponding function to define the pinname as an input or output. As I think, it might be improved in the future.