Re: [myhdl-list] a few questions relating to recursive designs

[Jan D. <ja...@ja...>]

Geoffrey Brown wrote:
> I thought I'd plunge in with a recursive structure (an N-way mux) which 
> follows.  I'm embarrassed
> how long it took me to figure this out.   Now here are a few questions.
> 
> 1)  I wanted to use a selector both as a bit vector and an integer.  
> Naturally
>    I made a signal from an intbv, but found the hard way that the obvious
>    thing, picking off bits by slicing, doesn't give you what is needed 
> (in this
>    context) -- another signal which has a subset of the bits from the 
> original
> 
>    I resorted to the (ugly) approach of passing an integer through the 
> hierarchy
>    so I could do the bit selection at the leaves.  Another ugly solution 
> would
>    be to define the selector as a list of signals and slice this up.  
> The problem
>    with this approach is that at the top level of the design one has to 
> bridge
>    from the single intbv to list of signals.

As other examples illustrate, recursive designs work quite well if you can
use lists of signals.
You can also use intbv Signals in recursion, but then you have to create
intermediate signals and the logic that drives them explicitly. So it
can be done, but this solution would indeed be rather ugly.

Your examples touch the area of MyHDL that I'm least satisfied with:
sometimes there is a valid need to consider the slice/index of a
signal as a signal itself. Currently, this can't be done and it
would require some new ideas/concepts in MyHDL. I would like to
see a breakthrough here and I have some ideas, but that is a
vast subject for separate thread.

>    Any thoughts on a more elegant approach ?
> 
> 2) It appears that to work with lists of signals, one must ensure that 
> at the
>     instance level the list has been unpacked into individual signals and at
>    the top level these lists are built from individual signals.    Is 
> this correct ?

First, any restrictions are related to convertibility, not modeling.

At the very top level, there is the problem that it's unclear how to
map lists of signals to Verilog ports. But again, this is only at the
top level of a design. In other words, it is possible that some module
cannot be converted as a top level design, but is perfectly convertible
within a hierarchy.

I'm not exactly sure what you mean with the restriction at the instance level.

Jan

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