Re: [myhdl-list] arithmetic trouble
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From: Jan D. <ja...@ja...> - 2009-05-16 06:46:10
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Neal Becker wrote: >> > > I suppose (not tested) that using systemverilog cast on the operands before > the operation to cast to the wider result type would fix it? Probably yes. How does this work, like resize in VHDL? Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com |