Re: [myhdl-list] arithmetic trouble

[Felton C. <chr...@gm...>]

> if that would be the best approach.  Or to simply restrict shifting.
>
> My time is severely limited right now as well.  If I find some free
> cycles I can try to methodically approach this issue.


Ok, I am going to get in trouble for being late to work.  But here is  
a quick cver simulation.  Just posting as FYI and info for others if  
interested.  What it shows, is that the Verilog simulator (at least  
cver, ?? how consistent are other simulators) will use the largest bit- 
width in the assignment, left or right hand side.

This "rule" would be hard to duplicate (if even desired) in MyHDL  
because the math operation doesn't know about the left-hand side. Some  
more thought and investigation is needed but this information might be  
useful for now.

Results
Left hand side is 8-bit (c16 == right hand 16 bit result).
123 = 248 + 255 --   251(c16) --         251(int)
   0 = 248 * 255 --   247(c16) --         247(int)
124 = 249 + 255 --   252(c16) --         252(int)
   0 = 249 * 255 --   248(c16) --         248(int)
124 = 250 + 255 --   252(c16) --         252(int)
   0 = 250 * 255 --   249(c16) --         249(int)
125 = 251 + 255 --   253(c16) --         253(int)
   0 = 251 * 255 --   250(c16) --         250(int)
125 = 252 + 255 --   253(c16) --         253(int)
   0 = 252 * 255 --   251(c16) --         251(int)
126 = 253 + 255 --   254(c16) --         254(int)
   0 = 253 * 255 --   252(c16) --         252(int)
126 = 254 + 255 --   254(c16) --         254(int)
   0 = 254 * 255 --   253(c16) --         253(int)
127 = 255 + 255 --   255(c16) --         255(int)
   0 = 255 * 255 --   254(c16) --         254(int)

Left hand side is 8bit and 'a' (i.e. a + b) is 16 bit
251 = 255 + 255 --   251(c16) --         251(int)
247 = 255 * 255 --   247(c16) --         247(int)
252 = 255 + 255 --   252(c16) --         252(int)
248 = 255 * 255 --   248(c16) --         248(int)
252 = 255 + 255 --   252(c16) --         252(int)
249 = 255 * 255 --   249(c16) --         249(int)
253 = 255 + 255 --   253(c16) --         253(int)
250 = 255 * 255 --   250(c16) --         250(int)
253 = 255 + 255 --   253(c16) --         253(int)
251 = 255 * 255 --   251(c16) --         251(int)
254 = 255 + 255 --   254(c16) --         254(int)
252 = 255 * 255 --   252(c16) --         252(int)
254 = 255 + 255 --   254(c16) --         254(int)
253 = 255 * 255 --   253(c16) --         253(int)
255 = 255 + 255 --   255(c16) --         255(int)
254 = 255 * 255 --   254(c16) --         254(int)
0 simulation events and 0 declarative immediate assigns processed.
242 behavioral statements executed (1 procedural suspends).
   Times (in sec.):  Translate 0.0, load/optimize 0.1, simulation 0.1.
   There were 0 error(s), 0 warning(s), and 1 inform(s).
End of GPLCVER_2.12a at Thu May 14 09:38:00 2009 (elapsed 0.0 seconds).

Simple TestBench
module test;

    integer i,j,x;
    reg [7:0] c;
    reg [15:0] c16;
    reg [7:0] a, b;
    reg [15:0] a16, b16;

    initial begin
       // 8 bit operands
       for(i=248; i<256; i=i+1) begin
	 for(j=255; j<256; j=j+1) begin
	    a = i;
	    b = j;
	    c   = (a + b) >> 1;
	    c16 = (a + b) >> 1;
	    x   = (i + j) >> 1;
	    $display("%d = %d + %d -- %d(c16) -- %d(int) ", c, a, b, c16, x);
	    c   = (a * b) >> 8;
	    c16 = (a * b) >> 8;
	    x   = (i * j) >> 8;
	    $display("%d = %d * %d -- %d(c16) -- %d(int)", c, a, b, c16, x);
	 end
       end // for (i=248; i<256; i=i+1)

       // a = 16 bit operand
       for(i=248; i<256; i=i+1) begin
	 for(j=255; j<256; j=j+1) begin
	    a16 = i;
	    b = j;
	    c   = (a16 + b) >> 1;
	    c16 = (a16 + b) >> 1;
	    x   = (i + j) >> 1;
	    $display("%d = %d + %d -- %d(c16) -- %d(int) ", c, a, b, c16, x);
	    c   = (a16 * b) >> 8;
	    c16 = (a16 * b) >> 8;
	    x   = (i * j) >> 8;
	    $display("%d = %d * %d -- %d(c16) -- %d(int)", c, a, b, c16, x);
	 end
       end
    end


endmodule