Re: [myhdl-list] arithmetic trouble

[Felton C. <chr...@gm...>]

>
>
>>
>> Should my_hdl try to workaround this?
>
> Yes - in the worst case it should refuse to convert shifts
> of expressions and suggest to use a temporary variable instead.
> Not ideal, but much better than simulation mismatches.
>
> I have no time right now to investigate these issues,
> I would appreciate if someone seeks this out systematically,
> ideally with more than one Verilog simulator (cver and
> icarus are free.)
>
> Jan
>

Well this could be an interesting problem, doing a little searching on  
google found this quote from another newsgroup (take it with a grain  
of salt)

"""
In Verilog, the width of the result of a binary operation is the  
maximum width of the operands. In your case, each operand is 8 bits so  
the result of the multiplication will be 8 bits. When you add the two  
8-bit numbers, the result will also be 8 bits.
"""

That statement agrees with what I recall (without looking up the  
Verilog standard) and the empirical results from your simulation.  The  
quick fix is to extend the result or one of the operands bit-widths  
(or the two step approach).

For the MyHDL fix the same rules could be enforced.  This is somewhat  
related to another thread which the intbv math operators return an  
intbv instead of an int.  I don't have the insight / opinion right now  
if that would be the best approach.  Or to simply restrict shifting.

My time is severely limited right now as well.  If I find some free  
cycles I can try to methodically approach this issue.