Re: [myhdl-list] arithmetic trouble

[Jan D. <ja...@ja...>]

Neal Becker wrote:


> 
> The problem is, it seems that (a * b) >>> 16 all in 1 step doesn't work 
> correctly.  I'm using cadence (version is 8.1?).  The simulator gives 
> strange results.  It seems to act as if it doesn't understand the bitwidth 
> of the intermediate result of (a*b), so that when shifted it's not correctly 
> handling the sign.
> 
> It works correctly if I break into 2 steps, where I use a tmp variable of 
> _the correct bit width_ before shifting.
> 
> Is this a common issue with verilog simulators, or is mine just broken?

Both are possible, though my guess is that your simulator works correctly
in terms of Verilog rules.

My guess is that we are being hit by Verilog's obscure rules for inferring
sizes and signedness. I would start by trying whether the bit width
of the left-hand side makes a difference. Perhaps the bit width of
the expression is reduced before the shift instead of after as it
"should" be.

> 
> Should my_hdl try to workaround this?

Yes - in the worst case it should refuse to convert shifts
of expressions and suggest to use a temporary variable instead.
Not ideal, but much better than simulation mismatches.

I have no time right now to investigate these issues,
I would appreciate if someone seeks this out systematically,
ideally with more than one Verilog simulator (cver and
icarus are free.)

Jan

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