Re: [myhdl-list] a few questions relating to recursive designs

[Felton C. <chr...@gm...>]

On May 13, 2009, at 3:31 PM, Geoffrey Brown wrote:

> I thought I'd plunge in with a recursive structure (an N-way mux)  
> which follows.  I'm embarrassed
> how long it took me to figure this out.   Now here are a few  
> questions.
>
> 1)  I wanted to use a selector both as a bit vector and an integer.   
> Naturally
>    I made a signal from an intbv, but found the hard way that the  
> obvious
>    thing, picking off bits by slicing, doesn't give you what is  
> needed (in this
>    context) -- another signal which has a subset of the bits from  
> the original
>
>    I resorted to the (ugly) approach of passing an integer through  
> the hierarchy
>    so I could do the bit selection at the leaves.  Another ugly  
> solution would
>    be to define the selector as a list of signals and slice this  
> up.  The problem
>    with this approach is that at the top level of the design one has  
> to bridge
>    from the single intbv to list of signals.
>
>    Any thoughts on a more elegant approach ?
>
> 2) It appears that to work with lists of signals, one must ensure  
> that at the
>     instance level the list has been unpacked into individual  
> signals and at
>    the top level these lists are built from individual signals.     
> Is this correct ?
>

Well I was going to suggest a list of signals was your best option,  
see the MyHDL below.  But there is a problem with this  
implementation.  The converters want to treat the list of signals (at  
least in this case) as memory.  It assumes that the input, A, is  
internal and not a port.

I still think a list of signals is your best option.   Personally I  
would like to see the list of signals be more generic, not always  
resulting in a memory conversion (see earlier posts).  But the issue  
is how to distinguish a memory model from a generic usage??  In this  
example a little too much freedom (IMO) was taken in the conversion,  
because port A was removed in the resulting Verilog.

If your example was to experiment with the recursive property and not  
simply a mux, I think you can experiment with 'A' and 'sel' being a  
list of signals.

from myhdl import *

def nmux(z, A, sel):
     """
     A    --  List of Signal
     z    --  select output, z type should be the same as the
              types in A
     sel  --  select the signal
     """

     @always_comb
     def muxlogic():
         z.next = A[int(sel)]

     return muxlogic


if __name__ == '__main__':

     N    = 23
     # Direct indexing example
     A    = [Signal(intbv(0)[1:]) for i in range(N)]
     sel  = Signal(intbv(0)[N:])
     z    = Signal(intbv(0)[1:])

     toVerilog(nmux, z, A, sel)