Re: [myhdl-list] arithmetic trouble

[Christopher F. <chr...@gm...>]

>
>
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> It works correctly if I break into 2 steps, where I use a tmp variable of
> _the correct bit width_ before shifting.
>
> Is this a common issue with verilog simulators, or is mine just broken?
>
> Should my_hdl try to workaround this?
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>
>
I don't recall the exact rules off the top of my head, either.  But I think
this is correct.  The language doesn't presume to know what the intermediate
bit representation of the operator is (Verilog language).  If you want full
precision for the multiply you have to do it in two steps as you indicated
or have your output be the full range.

BOMK everything is working correctly.  What you notice is a simulation
mismatch?  The MyHDL simulates fine because the * uses full precision
(infinite bits) and the bounds are not checked until the left hand side is
assigned and that is after the shift.   Hmmmm, don't know if this would be a
bug or not.  Not all aspects are convertible and this would fit that
scenario.