[myhdl-list] arithmetic trouble

[Neal B. <ndb...@gm...>]

I'm still learning verilog.  Anyway, I found the following problem.

------------------------------
from myhdl import Signal, always, intbv, Simulation, delay, toVerilog, 
traceSignals, instance, always_comb

def test1 (a, b, out):
    @always_comb
    def test1_logic():
        out.next = (a * b) >> 16

    return test1_logic

def max_signed (bits):
    return ~(-1 << (bits-1))

def min_signed (bits):
    return (-1 << (bits-1))

a = Signal (intbv(0, min_signed (16), max_signed (16)+1))
b = Signal (intbv(0, min_signed (16), max_signed (16)+1))
out = Signal (intbv(0, min_signed (16), max_signed (16)+1))

toVerilog (test1, a, b, out)

-----------------------------
module test1 (
    a,
    b,
    out
);

input signed [15:0] a;
input signed [15:0] b;
output signed [15:0] out;
wire signed [15:0] out;





assign out = $signed((a * b) >>> 16);

endmodule
-----------------------

The problem is, it seems that (a * b) >>> 16 all in 1 step doesn't work 
correctly.  I'm using cadence (version is 8.1?).  The simulator gives 
strange results.  It seems to act as if it doesn't understand the bitwidth 
of the intermediate result of (a*b), so that when shifted it's not correctly 
handling the sign.

It works correctly if I break into 2 steps, where I use a tmp variable of 
_the correct bit width_ before shifting.

Is this a common issue with verilog simulators, or is mine just broken?

Should my_hdl try to workaround this?