Re: [myhdl-list] hierarchy flattening on conversion to vhdl/verilog

[Christopher F. <chr...@gm...>]

>
> The loss of hierarchy seems unnecessary and makes it
> > harder to relate the output and input.
>

If this is desired for debug I imagine it is straight forward enough to have
a script to individually convert each "block".  You would have to manually
wire the top-level.  But it is an option.  For final generation I haven't
notice the flat hierarchy being an issue.


> Conversion after elaboration was the insight I needed to make
> conversion a feasible project for me. The python interpreter
> does as much work as possible and adds information
> without which I don't think it is even possible.


In my opinion this is one of the huge benefits of MyHDL (Python based HDL)
over the traditional HDLs.  There is a lot of power in this feature.