Re: [myhdl-list] the path not taken
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jandecaluwe
From: Jan D. <ja...@ja...> - 2009-04-24 19:06:19
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Neal Becker wrote: > I'm having a problem with this code: > > def rnd (x, bits, output): > min_val = x.min > max_val = x.max > @always_comb > def rnd_logic(): > if (bits < 1): > output.next = x > else: > y1 = intbv (int (x >> (bits-1)), min_val, max_val) > #y1 = intbv (int(x), min_val, max_val) > y2 = intbv (int (y1 + 1), min_val, max_val) > y3 = intbv (int (y2 >> 1), min_val, max_val) > output.next = y3 > return rnd_logic > > When translating to verilog: > ValueError: negative shift count > > If the commented line #y1 is used, no error. > > So myhdl is complaining about neg shift count if bits < 1, even though I > tried to eliminate that with the if (bits < 1). > > What can I do? I think the problem can be solved by making the code much clearer at the same time. I would separate object contruction from usage. Also, I would avoid using redundant objects and constructors - now they look like ugly type conversions. For example: def rndn (x, bits, output): min_val = x.min max_val = x.max @always_comb def rnd_logic(): y = intbv(0, min_val, max_val) if (bits < 1): output.next = x else: y[:] = x >> bits-1 y += 1 output.next = y >> 1 return rnd_logic -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com |