Re: [myhdl-list] Need instance name

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> I coded a function that, when synthesized, generates very poor verilog code.  
> So, I hand coded the verilog using __verilog__.  Problem is, that I coded 
> something like:
> 
> always @(%(x)s) begin
>     reg signed [%(inbits)s-1:0] y1;
>  ...
> 
> This gives a syntax error regarding unnamed blocks.  If I let myhdl code the 
> block, it would be a named block, using the instance name.
> 
> How can I get the instance name from my python code, so I could write 
> 
> always @(%(x)s) begin: <instance name>

The hierarchical name generated by MyHDL is internal, but surely you don't
need that one.
Just put a name there in the __verilog__ template. If parameterization
is needed, you can use any name from the surrounding namespace in the
template.

I suspect something else is going on though. I don't think named blocks
are used systematically by Verilog designers.

Jan

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