Re: [myhdl-list] missing declaration of input?

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> I found that I had to edit the verilog output, adding a signed declaration.  
> Ideas?

If the ranges of x are defined like you did:
  x = Signal (intbv(0)[37:0])

it is always going to be "unsigned" (as in Verilog).

If you want it "signed", you have to use min and max for x also.

Jan

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