[myhdl-list] missing declaration of input?
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jandecaluwe
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From: Neal B. <ndb...@gm...> - 2009-03-27 15:05:10
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I found that I had to edit the verilog output, adding a signed declaration.
Ideas?
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... def's of max_signed, min_signed
def sat_rnd (x, bits, outbits, out):
min_val = min_signed (len (x))
max_val = max_signed (len (x))
min_out = min_signed (outbits)
max_out = max_signed (outbits)
@always_comb
def sat_rnd_logic():
y1 = intbv (int (x >> (bits-1)), min_val, max_val)
y2 = intbv (int (y1 + 1), min_val, max_val)
y3 = intbv (int (y2 >> 1), min_val, max_val)
if (y3 > max_out):
out.next = max_out
elif (y3 < min_out):
out.next = min_out
else:
out.next = y3
return sat_rnd_logic
x = Signal (intbv(0)[37:0])
out = Signal (intbv (0)[18:0])
def verilog():
toVerilog.name = 'sat_rnd_36_18_18'
toVerilog (sat_rnd, x, 18, 18, out)
if __name__ == "__main__":
verilog()
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generated output:
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module sat_rnd_36_18_18 (
x,
out
);
input [36:0] x;
output [17:0] out;
reg [17:0] out;
wire signed [36:0] x; <<<<< NEED TO ADD THIS!!!
always @(x) begin: SAT_RND_36_18_18_SAT_RND_LOGIC
reg signed [37-1:0] y1;
reg signed [37-1:0] y3;
reg signed [37-1:0] y2;
y1 = (x >>> (18 - 1));
y2 = (y1 + 1);
y3 = $signed(y2 >>> 1);
if ((y3 > 131071)) begin
out <= 131071;
end
else if ((y3 < -131072)) begin
out <= -131072;
end
else begin
out <= y3;
end
end
endmodule
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