Re: [myhdl-list] MyHDL logic synthesis

[Jan D. <ja...@ja...>]

Newell Jensen wrote:

> So in the end....if I am going to make optimisations and go through the 
> trouble of fine tunning things hopefully there is a direct mapping in 
> the conversion.

There is, for working code.

> Just to see if this was so I went and tried to code up 
> the second example here in MyHDL.  I got it to convert fine, but what I 
> got fails during synthesis for Xilinx ISE 10.1 (service pack is the 
> latest as well).  This is my myhdl module and following it is the 
> conversion:

Newell, here's a golden advice for using conversion.

    http://www.myhdl.org/doc/0.6/manual/conversion.html#simulate-first

Until you are very experienced with MyHDL and conversion, please
simulate first. I agree that the conversion could do a better job of
catching common errors, but due to the nature of Python, it will
never do as good a job as a simulation. Unless simulation works,
all bets are off for the meaningfulness of conversion.

Below you are doing signal assignment on variables. You would get
a run-time error in simulation immediately.

Unlike Verilog, MyHDL makes a distinction between signals and variables.

Signals are used for communication between generators:
    http://www.myhdl.org/doc/0.6/manual/intro.html#signals-ports-and-concurrency

However, you can also use them in a single generator just to get their
parallel semantics, as your example suggests. But you still have to define
them outside the generator as usual. Alternatively, you can use variables
but then you have to control the order carefully.

For example, using your original example:

>     @always(clk.posedge)
>     def logic():
>         XPower1 = intbv(min=0, max=256)
>         XPower2 = intbv(min=0, max=256)
>         X1 = intbv(min=0, max=256)
>         X2 = intbv(min=0, max=256)
>         # Pipeline stage one
>         X1.next = X
>         XPower1.next = X
>         # Pipeline stage two
>         X2.next = X1
>         XPower2.next = XPower1 * X1
>         # Pipeline stage three
>         XPower.next = XPower2 * X2
>            
>     return logic
>    

With signal semantics:

    XPower1 = Signal(intbv(min=0, max=256))
    XPower2 = Signal(intbv(min=0, max=256))
    X1 = Signal(intbv(min=0, max=256))
    X2 = Signal(intbv(min=0, max=256))
 
    @always(clk.posedge)
    def logic():
        # Pipeline stage one
        X1.next = X
        XPower1.next = X        
        # Pipeline stage two
        X2.next = X1
        XPower2.next = XPower1 * X1
        # Pipeline stage three
        XPower.next = XPower2 * X2

With variable semantics:

    @always(clk.posedge)
    def logic():
        XPower1 = intbv(min=0, max=256)
        XPower2 = intbv(min=0, max=256)
        X1 = intbv(min=0, max=256)
        X2 = intbv(min=0, max=256)
        # Pipeline stage three
        XPower[:] = XPower2 * X2
        # Pipeline stage two
        X2[:] = X1
        XPower2[:]= XPower1 * X1
         # Pipeline stage one
        X1[:] = X
        XPower1[:] = X        
    

Both case should simulate, convert, and sythesize similarly.
(Interesting test!)

Jan
      

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as an HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com