Re: [myhdl-list] MyHDL logic synthesis

[Jan D. <ja...@ja...>]

Newell Jensen wrote:
> Jan,
> 
> Have you ever thought of giving MyHDL synthesis capabilities?

No.

Synthesis, the way I define it, would be a formidable task, certainly
beyond my capabilities as an open-source developer.

In addition to powerful HDL inference capabilites and logic minimization,
my definition of synthesis includes timing-driven optimization with an
integrated timing analyzer and powerful technology mapping, ideally
including placement info from an integrated P&R tool.

Morever, what would be the value proposition? Today I get these tools
basically for free from Xilinx and Altera for their architecture.

 > Icarus Verilog can synthesis designs and personally, I would find it a huge
> advantage to not have to go the MyHDL --> Verilog route as there are 
> many things that are not convertable such as delays etc.

I respect Stephen Williams very much and the value of Icarus the simulator
if very clear to me, including its tremendous value to the MyHDL project.
However, I don't see this for Icarus the synthesis tool.
I don't believe it matches my definition of a synthesis tool. It's kind of
hard to judge, as there is virtually no documentation that I can find,
but I'm pretty sure we would have heard about it otherwise.

So I suspect that after Icarus "synthesis" some other tool still has
to perform some tasks (e.g. timing optimization) that I consider part
of synthesis. In other words, it probably gives you an entry point
at a somewhat lower level than Verilog RTL, in a tool flow that you
have to run anyway, and which is basically free anyway.
Again, what's the point?

If I'm wrong, we can always wrap a synthesize() function around
the Icarus engine :-)

 From your question I infer that you assume that a direct synthesis
flow from MyHDL would somehow remove some synthesis-related restrictions
But that is not true. The restrictions would be just the same as
today. They are there for Icarus synthesis also, believe me.

However, those "synthesis restrictions" are in fact badly explained in
text books. So what could be meaningful is to write a guide for
"Efficient synthesis with MyHDL". (If I would do that, it would be
totally different from what you read today. I would basically start
with synchronous processes and flip-flop inferencing from variables.)

> I haven't looked into what would need to happen to make this happen but 
> I wanted to ask you to see what you thought about this.
> 
> Personaly, writing everything in Python would be a dream come true.

For all practical purposes, for me this dream is true today. After a project
is properly setup, conversion is hidden somewhere in a Makefile right before
synthesis. Verilog is just one of the many back-end formats used by the
back-end tools needed to go from MyHDL to an implementation. That's how
I see it, and it works fine.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
     http://www.myhdl.org