Re: [myhdl-list] MyHDL logic synthesis

[David B. <dav...@ya...>]

Yes,
 
I agree with Newell Jensen.  I believe a synthesis capability built within MyHDL would also be a dream come true.  
 
David Blubaugh

--- On Sat, 3/21/09, Newell Jensen <pil...@gm...> wrote:


From: Newell Jensen <pil...@gm...>
Subject: Re: [myhdl-list] MyHDL logic synthesis
To: "General discussions on MyHDL" <myh...@li...>
Date: Saturday, March 21, 2009, 10:16 PM





On Sat, Mar 21, 2009 at 6:37 PM, Newell Jensen <pil...@gm...> wrote:

Jan,

Have you ever thought of giving MyHDL synthesis capabilities?  Icarus Verilog can synthesis designs and personally, I would find it a huge advantage to not have to go the MyHDL --> Verilog route as there are many things that are not convertable such as delays etc.

After re-reading this I realize that using a delays wasn't a good example.
 



I haven't looked into what would need to happen to make this happen but I wanted to ask you to see what you thought about this.

Personaly, writing everything in Python would be a dream come true.

-- 
Newell



-- 
Newell


-----Inline Attachment Follows-----


------------------------------------------------------------------------------
Apps built with the Adobe(R) Flex(R) framework and Flex Builder(TM) are
powering Web 2.0 with engaging, cross-platform capabilities. Quickly and
easily build your RIAs with Flex Builder, the Eclipse(TM)based development
software that enables intelligent coding and step-through debugging.
Download the free 60 day trial. http://p.sf.net/sfu/www-adobe-com
-----Inline Attachment Follows-----


_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list