Re: [myhdl-list] MyHDL logic synthesis

[Newell J. <pil...@gm...>]

On Sat, Mar 21, 2009 at 6:37 PM, Newell Jensen <pil...@gm...> wrote:

> Jan,
>
> Have you ever thought of giving MyHDL synthesis capabilities?  Icarus
> Verilog can synthesis designs and personally, I would find it a huge
> advantage to not have to go the MyHDL --> Verilog route as there are many
> things that are not convertable such as delays etc.


After re-reading this I realize that using a delays wasn't a good example.


>
>
> I haven't looked into what would need to happen to make this happen but I
> wanted to ask you to see what you thought about this.
>
> Personaly, writing everything in Python would be a dream come true.
>
> --
> Newell
>



-- 
Newell