[myhdl-list] MyHDL logic synthesis

[Newell J. <pil...@gm...>]

Jan,

Have you ever thought of giving MyHDL synthesis capabilities?  Icarus
Verilog can synthesis designs and personally, I would find it a huge
advantage to not have to go the MyHDL --> Verilog route as there are many
things that are not convertable such as delays etc.

I haven't looked into what would need to happen to make this happen but I
wanted to ask you to see what you thought about this.

Personaly, writing everything in Python would be a dream come true.

-- 
Newell