Re: [myhdl-list] generate verilog with parameter statement

[Christopher F. <chr...@gm...>]

>
> How do I convert to verilog so that it will contain a 'parameter'
> statement?
>
> I want to specify a value via a verilog 'parameter'.  For example, I have a
> 'frame length' that will be passed to all modules via a verilog parameter.
> What would the corresponding myhdl source look like?
>
>
This isn't part of the standard conversion.  The philosophy is that your
complete design (for the most part) is implemented in MyHDL and that the
Verilog/VHDL is the output, similar to how netlists are generated by
synthesis tools but not, necessarily, directly used in the design.  There is
no conversion of the parameters since the generated code isn't intended to
be modular.  Other words the generated code is a direct representation of
the MyHDL after elaboration (after the parameters have been applied in
python etc).  See the conversion page for a better explanation than mine.

But it may not be practical to re-implement your design in MyHDL.  You may
want to start implementing some of the modules in MyHDL and incorporate it
to your design.  In that case, BOMK, you will have to use the "User-defined
code" (http://www.myhdl.org/doc/0.6/manual/conversion.html)<http://www.myhdl.org/doc/0.6/manual/conversion.html>,
__verilog__, to add the parameters you want.

Hope that helps, Good luck