Re: [myhdl-list] essay about integer arithmetic

[Christopher F. <chr...@gm...>]

>
> However, if we're talking about abstract behavior of numbers, how about
> some fixed-point support?  One of the nice things about VHDL is the
> ability to specify negative indicies that align with negative powers of
> 2.  Verilog doesn't (or at least didn't) provide even this level of support.
>
>
>  +1
>
> I would love to have a fixed-point type with arthimetic support.  It is a
> lot of book keeping and quite messy syntactically to add /subtract/multiply
> two fixed point numbers, especially when they have different fractional
> widths.  When adding/subtracting, for example, you have to zero pad the LSBs
> until the decimal points line up prior to adding.  Something like (in
> verilog):
>
> wire [DATA_WIDTH-1:0] result = data1 + { data2, {FRAC_WIDTH1 - FRAC_WIDTH2
> {1'b0}};
>
> Furthermore, you have to know up front which one is going to have more
> fractional bits so that you can pad the appropriate one.
>
>
I think this is one of the strong benefits of MyHDL / Python.  MyHDL
provides the basics building blocks for simulation and conversion.  You can
add your packages / modules that do all the book keeping for things like
fixed-point.  This probably isn't something that should be built into the
language but additional modules and packages that can be created.