Re: [myhdl-list] essay about integer arithmetic

[Lane B. <la...@ub...>]

Andrew Lentvorski wrote:
> Jan Decaluwe wrote:
>   
>> This is an essay that I wanted to write for a long time.
>> It describes what I think is wrong with integer arithmetic
>> in VHDL and Verilog, and why MyHDL provides a solution.
>>
>> Before releasing it to the general public, I'm interested
>> to hear what you think about it.
>>
>>     http://www.jandecaluwe.com/hdldesign/counting.html
>>     
>
> The essay sums up some of my gripes about the mishmash that is the whole 
> abstract behavior of numbers problem.  Nicely done.  I know that I'll 
> point more than a few newbies at it.
>
>
> I do have a bit of a gripe about statements like:
> "This situation would not persist without the widespread support of the 
> designer community."
>
> Ummmmm, no.  Most of the designers I know of hate the way a *lot* of 
> things are done in Verilog and VHDL.  Would we be using MyHDL if that 
> were not the case?  ;)  However, an individual designer has very limited 
> options to push back into these standards.  See SystemVerilog, for 
> example.  EDA vendors have a high incentive and large resources to 
> push/implement what is *profitable* to them--usefulness to the the user 
> is an orthogonal consideration.
>
>
> However, if we're talking about abstract behavior of numbers, how about 
> some fixed-point support?  One of the nice things about VHDL is the 
> ability to specify negative indicies that align with negative powers of 
> 2.  Verilog doesn't (or at least didn't) provide even this level of support.
>   
+1

I would love to have a fixed-point type with arthimetic support.  It is 
a lot of book keeping and quite messy syntactically to add 
/subtract/multiply two fixed point numbers, especially when they have 
different fractional widths.  When adding/subtracting, for example, you 
have to zero pad the LSBs until the decimal points line up prior to 
adding.  Something like (in verilog):

wire [DATA_WIDTH-1:0] result = data1 + { data2, {FRAC_WIDTH1 - 
FRAC_WIDTH2 {1'b0}};

Furthermore, you have to know up front which one is going to have more 
fractional bits so that you can pad the appropriate one.


Lane