Re: [myhdl-list] essay about integer arithmetic

[David B. <da...@we...>]

Jan Decaluwe wrote:
> Andrew Lentvorski wrote:
> 
>> However, if we're talking about abstract behavior of numbers, how about 
>> some fixed-point support?  One of the nice things about VHDL is the 
>> ability to specify negative indicies that align with negative powers of 
>> 2.  Verilog doesn't (or at least didn't) provide even this level of support.
>>
>> Writing, say, a delta-sigma modulator in any HDL language is kind of a 
>> pain because we don't have an abstract "fixed point number" that you can 
>> assert against.  Adding extra bits at either end to cover different 
>> issues (Did it overflow?  I need more integer bits.  Is the error too 
>> large?  I need more fractional bits.) is a pain when it interacts with 
>> sign bits.
> 
> I have no experience with this. Is there synthesis support for it?
> 

I haven't used that feature myself, but I believe it is synthesisable in 
VHDL.  It just allows indexes that don't start at 0.  However, I expect 
it would be a little awkward to use the same idea with intbv since 
negative indexes have a different meaning for slicing in Python.

>> Unrelated note: I *STILL* hate c.next = <some expression>
>>
>> The fact that c = <some expression> often silently does the wrong thing 
>> when you really meant c.next = <some expression> is very un-Pythonic.
>>
>> Did Python 3K enable some form of introspection that could do something 
>> about this?
> 
> Some MyHDL decorators (always_comb) use introspection already.
> So we could use them to do checks like the one you propose.
> Of course, this would only work when decorators are used to
> create generators.
> 
> Jan
> 
>