Re: [myhdl-list] essay about integer arithmetic

[Thomas H. <th...@ct...>]

Jan Decaluwe schrieb:
> This is an essay that I wanted to write for a long time.
> It describes what I think is wrong with integer arithmetic
> in VHDL and Verilog, and why MyHDL provides a solution.
> 
> Before releasing it to the general public, I'm interested
> to hear what you think about it.
> 
>     http://www.jandecaluwe.com/hdldesign/counting.html
> 
> 
> 
Jan,

let me say that I enjoyed your essay very much. I have done some designs
in VHDL but did not have to use arithmetic in the past, other than the
usual '+1' for counters.

MyHDL to the rescue when I had to implement a serial pipelined divider:
your article explains very well the issues that I could avoid with it.

-- 
Thanks,
Thomas