Re: [myhdl-list] inheriting from intbv

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> I thought maybe I'd make intbv work a bit more like I want, but deriving 
> from it.  As a test:
> 
> class intbv_s (intbv):
>     def __init__ (self, val, nrbits):
>         intbv.__init__ (self, val, min=min_signed (nrbits), max=max_signed 
> (nrbits)+1)
> 
> But this didn't convert properly to verilog:
> 
> ...
>     y1 = intbv_s($signed(acc1__sum >>> (4 - 1)), 10);
>     y2 = intbv_s((y1 + 1), 10);
>     y3 = intbv_s($signed(y2 >>> 1), 10);
> 
> Looking at _toVerilog.py, I wonder if there is a problem?  For example:
> 
> 
>         elif f is intbv:
> 
> There are at least some places where 'is' is used instead of isinstance.  Is 
> this intentional? 

The goal is indeed to make subclassing possible as you suggest, and support
it by the convertor.

However, I have not yet tried it or tested this myself, so there will be
bugs. I intend to fix this in short order, because I agree that it could
be very useful.

The code that you point to should not use isinstance but issubclass.
With that change, it seems to me it should work.

Warning: using subclassing to set min/max ranges should work, but
not to change intbv functionality - that is built-in in the convertor.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org