[myhdl-list] inheriting from intbv

[Neal B. <ndb...@gm...>]

I thought maybe I'd make intbv work a bit more like I want, but deriving 
from it.  As a test:

class intbv_s (intbv):
    def __init__ (self, val, nrbits):
        intbv.__init__ (self, val, min=min_signed (nrbits), max=max_signed 
(nrbits)+1)

But this didn't convert properly to verilog:

...
    y1 = intbv_s($signed(acc1__sum >>> (4 - 1)), 10);
    y2 = intbv_s((y1 + 1), 10);
    y3 = intbv_s($signed(y2 >>> 1), 10);

Looking at _toVerilog.py, I wonder if there is a problem?  For example:


        elif f is intbv:

There are at least some places where 'is' is used instead of isinstance.  Is 
this intentional?