Re: [myhdl-list] essay about integer arithmetic

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Hi Pieter,

Verilog functioned successfully for many years without a representation for
signedness. Adding signed bitfields to the language is really I think only a
form of syntatic sugar. It's not strictly necessary for hardware design.

There are no data types in hardware! Bits do what their hardware says to do,
and it may be completely unrelated to signedness, or even to values. The rules
of Verilog for arithmetic DO make sense: they do what hardware does, and that
is good. That is why software is different than hardware, and it's why HDLs
are completely different than computer programming languages.

Applying computer programming language models (such as data types) to hardware
is a very dangerous idea for efficient, high-performance hardware engineering
of logic. Programming models don't work the way hardware works.

Ranges of values due not define a bitwidth explicitly, they define it implicitly.

As a designer, I want complete and total control over the number of bits
represented in the (simulated or synthesized) hardware. A program should NOT
do that for me, because a computer program is too stupid to understand what I
want those bits to do, or to mean.

A collection of bits can well more than a single range in representation. A
32-bit register can represent 32 bit flags, each having a range [0,1]. Or it
could represent (4) 8-bit values, each having a range [0,255], [-128,127] or a
mix. Or it could represent two fields, (6) 1-bit flag values concatenated to a
26-bit ordinal. Or, or, or... any number of alternative representations
involving bit-level concurrency that cannot be represented with a single
interval specification. This kind of thing is done all the time in hardware.

I don't want to use several intervals to imply what I mean, I want to use a
single ordinal to say how many bits I want, their interpretation being
possibly completely unrelated to the number of bits as a total.

Use of intervals is being proposed as a means to imply bitwidth, and this is
an anathma to explicit, specific, user-defined design representation.

As a designer, I already know what I want the underlying hardware bit
representation to do, or to mean. A high-level HDL should get out of my way to
let me do that.

Hope this answers your queries with some additional amplification.

Best,
Michael

On Fri, 6 Mar 2009 14:22:59 +0100, Pieter wrote
> That's funny, only yesterday I saw someone write this:
> 
> some_signal <= '0'
> if ((a-b) = 1 or (b-a) = 1) then
>   some_signal <= '1';
> end if;
> 
> The arithmetic rules in Verilog are confusing and just wrong. The
> rules in VHDL are hard to grasp for students, but there's some logic
> behind it. If only the result of an operation would be as wide as the
> target, that would solve many issues. It doesn't feel right to change
> the size of the operand, to get the right size for the result. (and 
> of course you should be able to add a signed and an unsigned operand 
> without having to cast the unsigned to signed + adding a zero to the 
> front)
> 
> @ Michael Baxter
> I don't have a lot experience in hardware design. For me this doesn't
> feel like automating bit-widths. You still define max and min values
> for the intbev, so you declare the bit width explicitly. Isn't it
> about the arithmetic rules that are counter-intuitive? I can't see
> there's anything wrong with those of MyHDL, they are intuitive and
> create the hardware you want. Can you explain why you believe this
> automates bit widths and this should never be done?
> 
> kind regards,
> 
> pieter
> 
> 2009/3/6 Michael Baxter <ma...@cr...>:
> > IMHO, though informed with years of hardware implementation experience,
> > automating bit-widths should be 100% a non-goal. It should never be done under
> > any circumstances whatsoever.
> >
> > IMHO, this is a serious failing of MyHDL.
> >
> > Best,
> > Michael
> > California
> >
> > On Fri, 06 Mar 2009 07:21:50 -0500, Neal Becker wrote
> >> Jan Decaluwe wrote:
> >>
> >> > This is an essay that I wanted to write for a long time.
> >> > It describes what I think is wrong with integer arithmetic
> >> > in VHDL and Verilog, and why MyHDL provides a solution.
> >> >
> >> > Before releasing it to the general public, I'm interested
> >> > to hear what you think about it.
> >> >
> >> >     http://www.jandecaluwe.com/hdldesign/counting.html
> >> >
> >> >
> >> >
> >>
> >> If you really want to automate the bit widths, perhaps some kind of
> >> interval arithmetic is wanted?
> >>
> >> python mpmath and pyinterval both supply some interval arithmetic,
> >> but these are over reals, not integers.
> >>
> >>
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> -- 
> Pieter Cogghe
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> 9000 Gent
> 0487 10 14 21
> 
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