Re: [myhdl-list] essay about integer arithmetic

[Michael B. <ma...@cr...>]

IMHO, though informed with years of hardware implementation experience,
automating bit-widths should be 100% a non-goal. It should never be done under
any circumstances whatsoever.

IMHO, this is a serious failing of MyHDL.

Best,
Michael
California

On Fri, 06 Mar 2009 07:21:50 -0500, Neal Becker wrote
> Jan Decaluwe wrote:
> 
> > This is an essay that I wanted to write for a long time.
> > It describes what I think is wrong with integer arithmetic
> > in VHDL and Verilog, and why MyHDL provides a solution.
> > 
> > Before releasing it to the general public, I'm interested
> > to hear what you think about it.
> > 
> >     http://www.jandecaluwe.com/hdldesign/counting.html
> > 
> > 
> >
> 
> If you really want to automate the bit widths, perhaps some kind of 
> interval arithmetic is wanted?
> 
> python mpmath and pyinterval both supply some interval arithmetic, 
> but these are over reals, not integers.
> 
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