Re: [myhdl-list] AttributeError: '_ConvertFunctionVisitor' object has no attribute 'funcBuf'

[Neal B. <ndb...@gm...>]

I'm still getting my head around this verilog stuff.  I think it's working 
now.

If I want to translate something to verilog, I need to remember to write 
verilog-ish versions of all the functions it uses.

It seems myhdl will attempt to translate ordinary functions, but this might 
or might not work and might or might not produce a useful result.  I'm not 
sure under what circumstances this is actually what you want.

This seems to be correct code:
def max_signed (bits):
    return ~(-1 << (bits-1))

def min_signed (bits):
    return (-1 << (bits-1))

def extrema_signed (bits):
    return min_signed (bits), max_signed (bits)

def sat_rnd (x, bits, outbits, output):
    @always_comb
    def sat_rnd_logic():
        y1 = x >> (bits-1)
        y2 = y1 + 1
        y3 = y2 >> 1
        if (y3 > max_signed (outbits)):
            output.next = max_signed (outbits)
        elif (y3 < min_signed (outbits)):
            output.next = min_signed (outbits)
        else:
            output.next = y3

    return sat_rnd_logic
    


def Counter (count, clock, en, n, reset):
    @always (clock.posedge, reset.posedge)
    def cntLogic():
        if reset == 1:
            count.next = 0
        elif en:
            if count == n-1:
                count.next = 0
            else:
                count.next = count + 1

#        print "count:", count
    return cntLogic

def accum (x, result, count, clock, en, log2_n, reset):
    n = 1 << log2_n
    sumbits = log2_n + len (result)
    _sum = Signal (intbv(0, *extrema_signed (sumbits)))

    _sat_result = Signal (intbv (0, *extrema_signed (len (result))))
    _sat_rnd = sat_rnd (_sum, log2_n, len (result), _sat_result)
    
    @always (clock.posedge, reset.posedge)
    def accum_logic():
        if reset == 1:
            _sum.next = 0
            result.next = 0
        elif en:
            _sum.next = _sum + x
            if count == n-1:
                ##print 'count:', count, 'sum:', _sum
                result.next = _sat_result
                #result.next = _sum >> log2_n
                _sum.next = 0
                
    return accum_logic, _sat_rnd

def Decimator (clock, en, x, log2_n, count, result, reset):
    cnt1 = Counter (count, clock, en, 1 << log2_n, reset)
    acc1 = accum (x, result, count, clock, en, log2_n, reset)
    return cnt1, acc1

def to_hex (val):
    _hexdigits = '0123456789abcdef'
    digits = (val._nrbits + 3)/4
    s = []
    for i in xrange (digits-1, -1, -1):
        s.append (_hexdigits[(int(val) >> (4*i)) & 0xf])
    return ''.join (s)

def log2 (x):
    cnt = 0
    while x > 0:
        x >>= 1
        cnt += 1
    return cnt-1

def testbench(cosim=False):
    HALF_PERIOD = delay(1)

    clock = Signal (bool(0))
    x = Signal (intbv(10, *extrema_signed (6)))
    reset = Signal (bool(1))
    count = Signal (intbv(0)[4:])
    result = Signal (intbv(0, *extrema_signed (8)))
    en = Signal (bool(0))
    n = 16
    log2_n = log2 (n)
    
    if (cosim):
        from co import Decimator_v
        dut = Decimator_v (clock, en, x, log2_n, count, result, reset)
    else:
        dut = Decimator (clock, en, x, log2_n, count, result, reset)
    
    @always(HALF_PERIOD)
    def clockGen():
        clock.next = not clock

    
    @always(clock.posedge)
    def enGen():
        en.next = not en
        
    @instance
    def stimulus():
        while (1):
            yield clock.posedge
            ##x.next = 1
            reset.next = 0
        
    result_fd = file ('result', 'w')
    count_fd = file ('count', 'w')
    reset_fd = file ('reset', 'w')
    x_fd = file ('x', 'w')
    en_fd = file ('en', 'w')
    
    @instance
    def monitor():
        while 1:
            yield clock.posedge
            print 'reset:', reset, 'en:', en, 'x:', x, 'count:', 
to_hex(count), 'result:', to_hex(result)
            print >> result_fd, to_hex (result)
            print >> count_fd, to_hex (count)
            print >> x_fd, to_hex (x)
            print >> reset_fd, to_hex (reset)
            print >> en_fd, to_hex (en)
            
    return clockGen, enGen, stimulus, monitor, dut


def main():
   
    tb = traceSignals (testbench)
    #tb = testbench()

    Simulation(tb).run(100)

def cosim():
    tb = testbench(cosim=True)
    Simulation (tb).run (100)

def verilog():
    HALF_PERIOD = delay(1)

    clock = Signal (bool(0))
    x = Signal (intbv(0, *extrema_signed (6)))
    reset = Signal (bool(1))
    count = Signal (intbv(0)[4:])
    result = Signal (intbv(0, *extrema_signed (8)))
    en = Signal (bool(0))
    n = 16
    log2_n = log2 (n)
    toVerilog (Decimator, clock, en, x, log2_n, count, result, reset)