Re: [myhdl-list] cosimulation trouble

[Neal B. <ndb...@gm...>]

I seem to have it working now.  I have restructured things a bit.  Perhaps 
someone might comment on whether the style here is good/reasonable.

from myhdl import Signal, always, intbv, Simulation, delay, toVerilog, 
traceSignals, always_comb, instance



def Counter (count, clock, n, reset):
    @always (clock.posedge)
    def cntLogic():
        if reset == 1:
            count.next = 0
        elif count == n-1:
            count.next = 0
        else:
            count.next = count + 1

#        print "count:", count
    return cntLogic

def accum (x, result, count, clock, n, reset):
    _sum = Signal (intbv(0)[8:])
    
    @always (clock.posedge)
    def accum_logic():
        if reset == 1:
            _sum.next = 0
        else:
            _sum.next = _sum + x
            if count == n-1:
                ##print 'count:', count, 'sum:', _sum
                result.next = _sum
                _sum.next = 0

    return accum_logic

def Decimator (clock, x, n, count, result, reset):
    cnt1 = Counter (count, clock, n, reset)
    acc1 = accum (x, result, count, clock, n, reset)
    return cnt1, acc1

def testbench(cosim=False):
    HALF_PERIOD = delay(1)

    clock = Signal (bool(0))
    x = Signal (intbv(0)[4:])
    reset = Signal (bool(1))
    count = Signal (intbv(0)[4:])
    result = Signal (intbv(0)[8:])
    n = 16
    
    if (cosim):
        from co import Decimator_v
        dut = Decimator_v (clock, x, n, count, result, reset)
    else:
        dut = Decimator (clock, x, n, count, result, reset)
    
    @always(HALF_PERIOD)
    def clockGen():
        clock.next = not clock

    
    @instance
    def stimulus():
        while (1):
            yield clock.posedge
            x.next = 1
            reset.next = 0
        
    @instance
    def monitor():
        while 1:
            yield clock.posedge
            print 'reset:', reset, 'x:', x, 'count:', count, 'result:', 
result

    return clockGen, stimulus, monitor, dut


def main():
    tb = traceSignals (testbench)

    Simulation(tb).run(50)

def cosim():
    tb = testbench(cosim=True)
    Simulation (tb).run (50)

mode = 'sim'
#mode = 'test'
#mode = 'cosim'
#mode = 'verilog'

if __name__ == '__main__':
     if mode == "sim":
        main()
    elif mode == "cosim":
        cosim()

co.py:
from myhdl import *
from test3 import Decimator
import os

def Decimator_v(clock, x, n, count, result, reset):
    toVerilog(Decimator, clock, x, n, count, result, reset)
    cmd = "iverilog -o Decimator tb_Decimator.v Decimator.v"
    os.system (cmd)
    
    return Cosimulation("vvp -v -m ./myhdl.vpi Decimator", **locals())