Re: [myhdl-list] cosimulation trouble

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> Now I'm moving on to trying cosim.  I have installed icarus, compiled 
> myhdl.vpi.  When run with normal sim result is fine, but when run as cosim I 
> get no error, but nothing happens (I have a counter and an accumulator - the 
> count never increments and the accumulator output never changes).  Any 
> ideas?  Any hints at how to troubleshoot this?

Typically, the situation where "nothing happens" is caused by initialization
issues. In particular, in Verilog everything starts at 'X' by default, while
in MyHDL, the start value is defined.

In this case, I guess count starts at 'X', and as it is not explicitly
reset, it stays at 'X'. Also, no events are generated to the MyHDL side,
so count seems to keep its starting value.

The solution is to use an explicit reset signal that brings the circuit
into a known state.

At the RTL level and higher, the MyHDL convertor could in fact generate
initialization values with the Verilog declarations to bring the Verilog
code more in line with MyHDL at time 0. The only reason why this isn't
done it that at one point it was reported that some synthesis tools
don't support that (I think it was the tool from Altera). I'm interested
in hearing whether that's still the case.

At the gate level, you would always need the reset signal though.

Jan

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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
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