Re: [myhdl-list] assertion error in toVerilog

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> Christopher Felton wrote:
> 
>>>    @always (clock.posedge)
>>>    def accum_logic():
>>>        _sum.next += x
>>>        if count == n-1:
>>>            ##print 'count:', count, 'sum:', _sum
>>>            result.next = _sum
>>>            _sum.next = 0
>>>
>>>    return accum_logic
>>>
>>> Any ideas?
>>
>> The problem is the _sum.next += x
>>
>> Change to _sum.next = _sum + x
>>
>> Attached is the code that I successfully converted.
> Thank you so much for your help!
> 
> 2 questions:
> 1.
>  python test3.py
> ** ToVerilogWarning: Output port is read internally: count
> 
> What does this mean and should I worry?  Any way to tell what lines of code 
> this is coming from?

It means that count is an output port that is not only written,
but also read internally.

In Verilog and MyHDL, this is allowed without problems, although some
may argue it's not very clean. In VHDL, you cannot do this unless the output
port is declared as "inout", which some designers may want to avoid. Hence
the warning, so you know.

Jan


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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
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