[myhdl-list] cosimulation trouble

[Neal B. <ndb...@gm...>]

Now I'm moving on to trying cosim.  I have installed icarus, compiled 
myhdl.vpi.  When run with normal sim result is fine, but when run as cosim I 
get no error, but nothing happens (I have a counter and an accumulator - the 
count never increments and the accumulator output never changes).  Any 
ideas?  Any hints at how to troubleshoot this?

Here is the code:
from myhdl import Signal, always, intbv, Simulation, delay, toVerilog, 
traceSignals, always_comb, instance



def Counter (count, clock, n):
    @always (clock.posedge)
    def cntLogic():
        if count == n-1:
            count.next = 0
        else:
            count.next = count + 1

#        print "count:", count
    return cntLogic

def accum (x, result, count, clock, n):
    _sum = Signal (intbv(0)[8:])
    
    @always (clock.posedge)
    def accum_logic():
        _sum.next = _sum + x
        if count == n-1:
            ##print 'count:', count, 'sum:', _sum
            result.next = _sum
            _sum.next = 0

    return accum_logic

def Decimator (clock, x, n, count, result):
    cnt1 = Counter (count, clock, n)
    acc1 = accum (x, result, count, clock, n)
    return cnt1, acc1

def testbench(dut, clock, count, x, result):
    HALF_PERIOD = delay(1)

    
#    decimator1 = Decimator (clock, x, n, count, result)
    
    @always(HALF_PERIOD)
    def clockGen():
        clock.next = not clock

    @instance
    def stimulus():
        while (1):
            yield clock.posedge
            x.next = 1
        
    @instance
    def monitor():
        while 1:
            yield clock.posedge
            print 'x:', x, 'count:', count, 'result:', result

    return clockGen, stimulus, monitor, dut


def main():
    n = 16
    x = Signal (intbv(0)[4:])
    #clock = Signal()
    clock = Signal (intbv(0)[1:])
    result = Signal(intbv(0)[8:])
    count = Signal (intbv(0)[4:])
    dut = Decimator (clock, x, n, count, result)
    tb = traceSignals (testbench, dut, clock, count, x, result)

    Simulation(tb).run(50)

def cosim():
    n = 16
    x = Signal (intbv(0)[4:])
    #clock = Signal()
    clock = Signal (intbv(0)[1:])
    result = Signal(intbv(0)[8:])
    count = Signal (intbv(0)[4:])
    from co import Decimator_v
    dut = Decimator_v (clock, x, n, count, result)

    tb = testbench (dut, clock, count, x, result)
    Simulation (tb).run (50)
#mode = 'sim'
#mode = 'test'
mode = 'cosim'

if __name__ == '__main__':
    if (mode == 'verilog'):
         n = 16 
         x      = Signal(intbv(0)[4:]) 
         clock  = Signal(False) 
         result = Signal(intbv(0)[8:]) 
         count  = Signal(intbv(0)[4:]) 

         #dut = Decimator (clock, x, n, count, result) 
         toVerilog(Decimator, clock, x, n, count, result) 
    elif mode == "test":
        toVerilog (testbench)
    elif mode == "sim":
        main()
    elif mode == "cosim":
        cosim()

And here is co.py:
from myhdl import *
from test3 import Decimator
import os

def Decimator_v(clock, x, n, count, result):
    toVerilog(Decimator, clock, x, n, count, result)
    cmd = "iverilog -o Decimator tb_Decimator.v Decimator.v"
    os.system (cmd)
    
    return Cosimulation("vvp -v -m ./myhdl.vpi Decimator", **locals())

Here's what I get when mode = 'sim':
python test3.py
x: 0 count: 0 result: 0
x: 1 count: 1 result: 0
x: 1 count: 2 result: 0
x: 1 count: 3 result: 0
x: 1 count: 4 result: 0
x: 1 count: 5 result: 0
x: 1 count: 6 result: 0
x: 1 count: 7 result: 0
x: 1 count: 8 result: 0
x: 1 count: 9 result: 0
x: 1 count: 10 result: 0
x: 1 count: 11 result: 0
x: 1 count: 12 result: 0
x: 1 count: 13 result: 0
x: 1 count: 14 result: 0
x: 1 count: 15 result: 0
x: 1 count: 0 result: 14
x: 1 count: 1 result: 14
x: 1 count: 2 result: 14
x: 1 count: 3 result: 14
x: 1 count: 4 result: 14
x: 1 count: 5 result: 14
x: 1 count: 6 result: 14
x: 1 count: 7 result: 14
x: 1 count: 8 result: 14
<class 'myhdl._SuspendSimulation'>: Simulated 50 timesteps

For mode = 'cosim':

 python test3.py
** ToVerilogWarning: Output port is read internally: count
Compiling VVP ...
 ... VVP file version 0.9.devel (s20080905-418-g1c17412)
Compile cleanup...
 ... Linking
 ... Removing symbol tables
 ... Compiletf functions
 ...       10 functors (net_fun pool=0 bytes)
                  0 logic
                  0 bufif
                  0 resolv
                  9 signals
 ...       42 opcodes (24576 bytes)
 ...        9 nets
 ...       10 vvp_nets (1048560 bytes)
 ...        0 arrays (0 words)
 ...        0 memories
                  0 logic (0 words)
                  0 real (0 words)
 ...        4 scopes
 ... 0.001 seconds, 36420.0/3340.0/1296.0 KBytes size/rss/shared
Running ...
x: 0 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
<class 'myhdl._SuspendSimulation'>: Simulated 50 timesteps
 ... 0.002 seconds, 36420.0/3496.0/1448.0 KBytes size/rss/shared
Event counts:
         203 time steps (pool=146)
         128 thread schedule events
          55 assign events
             ...assign(vec4) pool=9362
             ...assign(vec8) pool=204
             ...assign(real) pool=256
             ...assign(word) pool=128
         353 other events (pool=4096)