Re: [myhdl-list] assertion error in toVerilog

[Christopher F. <chr...@gm...>]

>
>
> 2 questions:
> 1.
>  python test3.py
> ** ToVerilogWarning: Output port is read internally: count
>
> What does this mean and should I worry?  Any way to tell what lines of code
> this is coming from?


I did not scrutinize the Verilog output.  For this exercise I was content
when the converter ran without error.  I do not know what the error is with
out greping for the error string.


>
>
> 2.
> I noticed you changed:
>     @always (clock.posedge)
>    def accum_logic():
>         _sum.next = _sum + x
>         if count == n-1:
>            ##print 'count:', count, 'sum:', _sum
>            result.next = _sum
>            _sum.next = 0
>
>   return accum_logic
>
> to
>
>   @always (clock.posedge)
>     def accum_logic():
>          _sum.next = _sum + x
>         if count == n-1:
>             #result.next = _sum
>             _sum.next = 0
>
>     @always (clock.posedge)
>     def rtl():
>         if count == n-1:
>             result.next = _sum
>
>     return accum_logic, rtl
>
> Any significance to this change?
>
>
Sorry, the changes are not significant.  I was just testing a couple
different things.  I randomly tried a couple things before analyzing the
signal that was being asserted (printing the sig in _analyze.py).  I never
put the code back to the original structure.  Before modifying _analyze.py
to print more info I was trying to get some more information.