Re: [myhdl-list] assertion error in toVerilog

[Neal B. <ndb...@gm...>]

Christopher Felton wrote:

>>
>>    @always (clock.posedge)
>>    def accum_logic():
>>        _sum.next += x
>>        if count == n-1:
>>            ##print 'count:', count, 'sum:', _sum
>>            result.next = _sum
>>            _sum.next = 0
>>
>>    return accum_logic
>>
>> Any ideas?
> 
> 
> The problem is the _sum.next += x
> 
> Change to _sum.next = _sum + x
> 
> Attached is the code that I successfully converted.
Thank you so much for your help!

2 questions:
1.
 python test3.py
** ToVerilogWarning: Output port is read internally: count

What does this mean and should I worry?  Any way to tell what lines of code 
this is coming from?

2.
I noticed you changed:
    @always (clock.posedge)
    def accum_logic():
        _sum.next = _sum + x
        if count == n-1:
            ##print 'count:', count, 'sum:', _sum
            result.next = _sum
            _sum.next = 0

   return accum_logic

to

   @always (clock.posedge) 
     def accum_logic(): 
         _sum.next = _sum + x 
         if count == n-1: 
             #result.next = _sum 
             _sum.next = 0 
 
     @always (clock.posedge) 
     def rtl(): 
         if count == n-1: 
             result.next = _sum 
             
     return accum_logic, rtl 
 
Any significance to this change?