Re: [myhdl-list] assertion error in toVerilog

[Christopher F. <chr...@gm...>]

from myhdl import *

def Counter (count, clock, n):
    @always (clock.posedge)
    def cntLogic():
        if count == n-1:
            count.next = 0
        else:
            count.next = count + 1

    return cntLogic

def accum (x, result, count, clock, n):
    _sum = Signal(intbv(0)[8:])
    
    @always (clock.posedge)
    def accum_logic():
        _sum.next = _sum + x
        if count == n-1:
            #result.next = _sum
            _sum.next = 0

    @always (clock.posedge)
    def rtl():
        if count == n-1:
            result.next = _sum
            
    return accum_logic, rtl

def Decimator (clock, x, n, count, result):
    cnt1 = Counter(count, clock, n)
    acc1 = accum(x, result, count, clock, n)
    return cnt1, acc1

if __name__ == '__main__':
    n = 16
    x      = Signal(intbv(0)[4:])
    clock  = Signal(False)
    result = Signal(intbv(0)[8:])
    count  = Signal(intbv(0)[4:])
    
    #dut = Decimator (clock, x, n, count, result)
    toVerilog(Decimator, clock, x, n, count, result)