Re: [myhdl-list] assertion error in toVerilog

[Christopher F. <chr...@gm...>]

>
> tb = toVerilog (testbench)
>
> def main():
>    Simulation(tb).run(50)
>
> if __name__ == "__main__":
>    main()
>
> Any ideas?
>
>
Not sure if this is your specific issue, you may want to try and only
convert the design to Verilog.  Converting testbenches is a newer feature of
the latest release.  Below is an snippet of an example only converting the
design and not the testbench.  There are a bunch of examples in the cookbook
and the user project area.

    #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    # Signals
    clk = Signal(False)
    rst = Signal(False)

    x = Signal(intbv(0, min=-L, max=L))
    y = Signal(intbv(0, min=minV, max=maxV))

    dvi = Signal(True)
    dvo = Signal(False)

    xcnt  = Signal(0)
    N_CLK = 0

    #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    # Instantiate MyHDL simulation and coversion functions
    if run == 'trace':
        dut = traceSignals(cic, clk, rst, x, dvi, y, dvo, M, D, R)
    elif run == 'ver':
        toVerilog(cic, clk, rst, x, dvi, y, dvo, M, D, R)
        return None
    elif run == 'vhd':
        toVHDL(cic, clk, rst, x, dvi, y, dvo, M, D, R)
        return None
    else:
        dut = cic(clk, rst, x, dvi, y, dvo, M, D, R)