[myhdl-list] assertion error in toVerilog

[Neal B. <ndb...@gm...>]

Traceback (most recent call last):
  File "test3.py", line 65, in <module>
    tb = toVerilog (testbench)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", line
115, in __call__
    genlist = _analyzeGens(arglist, h.absnames)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
160, in _analyzeGens
    compiler.walk(ast, v)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 106, in walk
    walker.preorder(tree, visitor)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 63, in preorder
    self.dispatch(tree, *args) # XXX *args make sense?
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
939, in visitModule
    self.visit(node.node)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 40, in default
    self.dispatch(child, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
998, in visitFunction
    self.visit(node.code)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 40, in default
    self.dispatch(child, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
486, in visitAugAssign
    self.visit(node.node, _access.INOUT)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
632, in visitGetattr
    self.visit(node.expr, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
743, in visitName
    raise AssertionError
AssertionError

Here is code:
from myhdl import Signal, always, intbv, Simulation, delay, toVerilog,
traceSignals, always_comb, instance



def Counter (count, clock, n):
    @always (clock.posedge)
    def cntLogic():
        if count == n-1:
            count.next = 0
        else:
            count.next = count + 1

        print "count:", count
    return cntLogic

def accum (x, result, count, clock, n):
    _sum = Signal (intbv(0)[8:])
    
    @always (clock.posedge)
    def accum_logic():
        _sum.next += x
        if count == n-1:
            ##print 'count:', count, 'sum:', _sum
            result.next = _sum
            _sum.next = 0

    return accum_logic

def Decimator (clock, x, n, count, result):
    cnt1 = Counter (count, clock, n)
    acc1 = accum (x, result, count, clock, n)
    return cnt1, acc1

def testbench():
    HALF_PERIOD = delay(1)

    n = 16
    x = Signal (intbv(0)[4:])
    #clock = Signal()
    clock = Signal (intbv(0)[1:])
    result = Signal(intbv()[8:])
    count = Signal (intbv(0)[4:])
    
    decimator1 = Decimator (clock, x, n, count, result)
    
    @always(HALF_PERIOD)
    def clockGen():
        clock.next = not clock

    @instance
    def stimulus():
        while (1):
            yield clock.posedge
            x.next = 1
        
    @instance
    def monitor():
        while 1:
            yield clock.posedge
            print 'x:', x, 'count:', count, 'result:', result

    return clockGen, stimulus, decimator1, monitor


tb = toVerilog (testbench)

def main():
    Simulation(tb).run(50)

if __name__ == "__main__":
    main()

Any ideas?