[myhdl-list] [newb] traceSignals question

[Neal B. <ndb...@gm...>]

In the following simple test:

from myhdl import Signal, always, intbv, Simulation, delay, toVerilog,
traceSignals

def ClkDriver(clk):

    halfPeriod = delay(1)

    @always(halfPeriod)
    def driveClk():
        clk.next = not clk

    return driveClk

def Counter (count, clock, n):

    @always (clock.posedge)
    def cntLogic():
        if count == n-1:
            count.next = 0
        else:
            count.next = count + 1

        print count
    return cntLogic

n = 16

count = Signal (intbv(0)[4:])
clock = Signal (bool())

#clkdriver_inst = ClkDriver(clock)
clkdriver_inst = traceSignals (ClkDriver, clock)
cnt_inst = Counter (count, clock, n)

sim = Simulation (clkdriver_inst, cnt_inst)
sim.run(50)

I assumed (it really isn't explained in the manual) that
traceSignals (ClkDriver, clock) would only trace signals used by 'ClkDriver',
which would only be clock.  It seems my .vcd output includes others, such as
'count'.  How is this determined?  Am I using traceSignals correctly?