Re: [myhdl-list] toVerilog conversion question

[Jan D. <ja...@ja...>]

Newell Jensen wrote:
> All,
> 
> I am trying to create a case statement in Verilog that relies on other 
> Signals such as this:
> (THIS WOULD BE THE VERILOG AFTER CONVERSION, where dwb_mx is a Signal 
> that is 32 bits)
> 
>     4'h8: mem_mx <= #1 {24'd0, dwb_mx[31:24]};
>     4'h4: mem_mx <= #1 {24'd0, dwb_mx[23:16]};
>     4'h2: mem_mx <= #1 {24'd0, dwb_mx[15:8]};
>     4'h1: mem_mx <= #1 {24'd0, dwb_mx[7:0]};
>     . . .
>     . . .
>     . . .
> 
> Is there a way to do this?  I have been struggling to get my conversion 
> to something like this and was wondering if it is possible.  All the 
> examples that I looked at online are case statements that already know 
> the values on the right side of => .  That is, when the tuple is made 
> with constants.  I guess I could do a bunch of if statements... but 
> didn't know if there was another way to do this more elegantly within MyHDL.

There are two separate cases when the convertor uses case statements:

1) to implement indexing into a tuple of constant integers
This is not what you're after here.

2) when it detects that the conditions in an if-elsif-esle control
structure are exclusive.
This is what you're after. I'm going to expand on this further.

As Python doesn't have a case statement, the straightforward way is to
map MyHDL if/elsif statements to Verilog if/elsif statements. The only
good reason to use case statements (+ pragmas) instead is because in
that way you can express exclusivity, which may result in a more
efficient implementation.

Currently, the convertor doesn't try to detect exclusivity based on
numbers. I don't think that would be very worthwhile. Instead, MyHDL
supports enumeration types, which let you express exclusive conditions
explicitly, like in VHDL.

When I look at your code, it seems it's trying to express one-hot
encoding. In my opinion, it's clearer and less error-prone to use
an enum type to represent the choices symbolically, and define
(or change!) the desired encoding at a single place in the code.
The enum type constructor has a parameter for this.

The documentation (see link below) is perhaps a little confusing.
It suggest that this optimization is only for FSMs. While that
is an important application, the optimization is actually general.
Whenever a enum type is used to indicate exclusivity in a control
structure, a case statement will be used in Verilog or VHDL.
It doesn't matter what you do inside the control structure.

http://www.myhdl.org/doc/0.6/manual/conversion_examples.html#optimizations-for-finite-state-machines

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a hardware description language:
     http://www.myhdl.org