Re: [myhdl-list] Another newbie question

[Jan D. <ja...@ja...>]

Newell Jensen wrote:
> All,
> 
> Is there a way to delay signals when converting to Verilog?

Not at this point.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a hardware description language:
     http://www.myhdl.org